SUNFEST REU Program IMPLEMENTATION OF THE ENIAC ACCUMLATOR AND CYCLING UNIT ON A FIELD PROGRAMMABLE GATE ARRAY (FPGA)

An accumulator and cycling unit from the Electronic Numerical Integrator and Calculator (ENIAC) are implemented on a Field Programmable Gate Array (FPGA). The FPGA implementation is not architecturally identical to the original ENIAC, but the original architectural design is maintained where possible. The design maintains decimal number representation, ring counters to increment numbers, and ten different clocks to coordinate various accumulator functions. The implementation is a preliminary step in the design of a series of FPGAs that will include a constant transmitter, three accumulators, be connected to panels similar to those of the original ENIAC and be an exact replica in the programmer's experience.